This invention relates to the field of solid state electronics, and particularly to a single-level photoresist process for producing metal-semiconductor field-effect transistors (MESFETs) with submicron gates and with uniform threshold voltages.
MESFETs used in integrated circuits require precise control of threshold voltage in order to obtain good performance and large-scale integration. It is necessary to obtain the targeted threshold voltage on wafers cut from different boules (boule to boule uniformity) and on wafers cut from a single boule. The across-wafer uniformity is limited by surface nonuniformities that are introduced by integrated circuit processing such as wet recessing.
Several self-alignment implantation processes have been published for fabricating submicron gate MESFETs. A tri-level resist process (K. Yamasaki, et al., ELECTRONIC LETTERS, Vol. 18, pp. 119-121, 1982) has been used to deposit a T-bar shaped dummy gate consisting of photoresist, sputtered- SiO.sub.2 and PMMA. The bottom layer of the gate (FPM) is undercut using reactive ion etching. Undercutting to form the T-bar shape is done before implanting the N.sup.+ regions and before depositing the SiO.sub.2 dielectric. This T-shape shields a fringe portion of the underlying N.sup.- channel during N.sup.+ implantation, while still allowing later deposition of the SiO.sub.2 dielectric over the N.sup.+ region, the N.sup.+ /N.sup.- interface, and the shielded portions of the N.sup.- channel.
A dual-level resist process (M. F. Chang et al, IEEE ELECTRON DEVICE LETTERS, Vol. EDL-6, No. 6, June 1985) uses photoresist and PMMA to develop a T-bar shaped dummy gate. Instead of undercutting the dummy gate by receiving ion etching as described above, a deep ultraviolet exposure of the PMMA is used to provide undercutting. As in the Yamasaki, et al process, undercutting is done before implanting the N.sup.+ regions so that the top of the dummay gate protects a fringe around the reduced gate from N.sup.+ implantation. A dry gate recessing process for achieving uniform threshold voltage is mentioned, but details of the process are not given.
A process which uses an SiO.sub.2 dummy gate that is covered with a photoresist (M. Hagio, et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-33, No. 6, June 1986) relies upon sidewall deposition (and later removal) of Si.sub.3 N.sub.4 on the dummy gate to provide a separation gap (or fringe) between the dummy gate and the N.sup.+ region.
Although prior art methods are capable of producing MESFETs with submicron gates, a continuing need exists for methods which are more economical, reliable, and which provide uniform threshold voltages for the many MESFETs in a single integrated circuit.